Single-ended data sensing is commonly used in memory arrays in which a memory cell (e.g., a transistor) is coupled to a capacitor and a bit line. The memory cell, when being invoked for reading, is required to discharge the bit line capacitance in a certain time period (e.g., an evaluation period before reading). For example, in some approaches, the memory cell is required to discharge (e.g., to pull the voltage level of) the bit line from the operation voltage Vdd to below the trip-point voltage of an inverter in the next reading stage. The evaluation period is the time it takes for the memory to discharge. The trip-point voltage is the voltage at which the inverter changes its state. Accurately reading the data, in effect, depends on the strength (e.g., the current driving/pulling capabilities) of the memory cell. In many applications (e.g., in high density memory arrays with multi-million memory cells/bits), the memory cell is inherently very small with low current driving capabilities (e.g., in the range of 20-30 μA). In some approaches, when the evaluation period is short and/or the current of the memory cell is weak, e.g., due to a weak cell, in a leakage process, or when the operation voltage is low (e.g., at the minimum required operation voltage (Vccmin) applications), the memory cell cannot completely discharge the bit line to the required voltage within the evaluation period, which results in incorrect read data.
Like reference symbols in the various drawings indicate like elements.